Vtyjkyuk

I want to ask about the

• PDP-6


• PDP-10
  
  
  • various implementations KA-10, KI-10, KL-10
  
  


• DECSYSTEM-20

What are the differences between these? I'm not that interested in architectural differences, cache sizes, etc. I'm most interested in the differences that could feasibly trip up an assembly language programmer.
Things like the instruction set, register set and so on, how these varied from machine to machine.

Bonus points if you also include the Foonly machines and other clones.

What are the differences between these? I'm not that interested in architectural differences, cache sizes, etc. I'm most interested in the differences that could feasibly trip up an assembly language programmer.

TL;DR: No.

For user side assembly programmers next to none - at least until the KL. UUOs (*1) did hide add ons for backward compatibility or non existence anyway, and TOPS-10/20 did offer a whole bucket of duplicate system calls depending on which address mode was used, thus software compatibility was rather high from beginning to end.

PDP-6

The original design, notoriously unreliable and hard to sell.

The main (hardware) design idea was kind of a bitslice implementation with 36 identical boards, each holding all circuitry needed for ALU and register and memory access for one bit plus communication in between and memory. About 100 transistors on a roughly A4 sized PCB.

PDP-10

Basically an unmodified update using improved components. PDP-6 programs could run unmodified. The new name was rather meant to get rid of the bad reputation the PDP-6 had, then based on (user side) differences.

Main add on on the software side was the introduction of a high memory segment register pair, allowing a second memory region for every user program, usable for shared memory, or kind of user swappable data segments (*2).

KA-10

First implementation. The main difference to the PDP-6 was being based on DEC Flipchip modules instead of the huge one board per bit design.

KI-10

22 bit physical address, plus paged virtual memory. Again not incompatibility with existing user code. On the system side of course, the new features where available and 18 bit user addresses (*3)had to be mapped onto the 22 bit physical address space. Similar sorting tasks to either CPU of the biprocessor did need new code.

KL-10

First to be called DECsystem-10. Also implemented in ECL. Through a changed internal structure some execution speed changed relative to others. But unless one counted cycles (in a virtual memory system somewhat fruitless anyway), no user level difference with KA or KI.

DECSYSTEM-20

Not really a different machine. When a KL-10 got sold with TOPS-20 it was called DECsystem-20. While DECsystem-10 system CPUs where named 10xx, the very same components did end up in DECsystem-20 CPUs (20xx). For example, a 1090 was essentially the same machine as a 2060. Then again, as James Large pointed out: "Different color cabinets though".

A real user side visible difference came with the

MODEL B CPUs

Here the 18 bit user address restriction was removed. All prior KL-10 CPUs cut of the address calculation at 18 bit. Now a user program could use the whole 36 bit address range. Due some kind of 'segments' which used the 4 register bits and the indirect bit(*4). A potential trap for old programs. This also lead to huge confusion with duplicate OS-calls depending on what address format was used and so on.

The last variant would be the infamous

KS-10

Essentially a Model B CPU without the segmented memory feature. Maybe they intended to replace older PDP-10 here or open up a low end market, in the end, no-one bought them, as the KS CPUs weren’t really cheap either, and could only run TOPS-10.

Bonus points if you also include the Foonly machines and other clones.

The Foonly-1 is basically a KA-10 on steroids. Much like the KL-10. In fact, they are quite related, as they come from partly the same team. It's a bit like as 8080 and Z80 - if some of the Z80 engineers would have returned to Intel again. The goal was to make the fastest PDP-10 possible. It was based on an advanced microprogram architecture and ECL logic. The result was about 4 times faster than the original KA series. And they made DEC working hard to compete with the KL-10 still being only half as fast. On the long run, they couldn't keep up. As usual with compatible manufacturers, where just making the faster the CPU isn't the whole business.

While the Foonly was meant as a competition, next to all other clones were targeted as PDP-10 replacements, after DEC cancelled the line in 1983(?). Systems Concepts with their SC-20/25/30 machines maybe the most well known. They where design was 100% compatible, faster than DEC (but slower than the Foonly-1), consumed less power and packed all in much smaller in size. Just they came late. At the time they could deliver, DEC had already convinced many users to switch for their VAX line. The only real success came with what was eventually the largest PDP-10 user of all times: Compuserve, as for them the cost of converting their software was way too high. AFAIR, Compuserve even started to build their own clones based on the SC-30 design to keep their business running way into the 1990s until their demise.

Similar XKL's TOAD system of the mid 1990s was meant as a PDP-10 replacement for die hard users. I have no idea how well they sold.

There where also other projects, but AFAIK they never reached commercial stage.

*1 - UUO: Undefined User Operations. Opcodes not recognized by hardware did end up in a trap, so the OS could either handle the error or emulate whatever function was needed. Also OS-Calls where made that way.

*2 - 'Virtual' memory was done with a set of two registers called base and boundary. Base did hold the real memory address that was mapped at program address zero, while boundary did hole the highest possible address (length). The PDP-10 just added a second set, which was selected by the highest address bit.

*3 - Address calculation on the PDP-6/10 was an interesting beast. While a basic instruction address field featured a register/offset combination (plus indirect bit), much like on a IBM /360, just 4+18 here, the resulting address was again limited to 18 bits (256 KiWords). A feature inherently coded in many TOPS-10 OS calls, requiring a compatibility layer for TOPS-20.

*4 - Never really looked into it, so whoever knows more, please step forward.